A high efficient hardware architecture for multiview 3DTV

There are three main challenges to design an efficient multiview 3DTV SoC:(1)how to organize DRAM address mapping to maximize off-chip bandwidth utilization;(2)how to design a parallel configurable image scaling engine to interpolate various viewpoints in real-time; (3)how to reduce computational complexity of float-point sub-pixel rearrangement with sufficient accuracy. To this end, we present a highly optimized hardware architecture, which saves 38.4% logic and 37.5% memory resources when implementing a multiview 1080P@60Hz 3DTV on the Xilinx XC5VLX330 FPGA.