Traffic Aware Scheduling Algorithm for Network on Chip

Steady advancements in semiconductor technology over the past few decades have lead to researchers have proposed network-on-chip (NoC) as the on-chip communication model. An efficient NoC design methodology is based upon several key design choices, such as: network topology selection, good routing policy and efficient application to NoC mapping. In this paper a novel off-line non-preemptive static traffic aware scheduling (TAS) policy is proposed for hard NoC platforms. The proposed scheduling policy maps the application onto the NoC architecture keeping track of the network traffic, which is generated with every resource and communication path allocation. The main contribution of the proposed algorithm is that the application mapping and scheduling process are handled together and inter-process communication latency are dynamically calculated based on the application mapping and PE interaction. Our TAS algorithm has been evaluated for various design metrics such as application completion time, resource utilization and task throughput. Simulation results show significant improvements over traditional approaches.