An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Author

Beer, Salomon ; Ginosar, Ran ; Priel, Michael ; Dobkin, Rostislav ; Kolodny, Avinoam

Author_Institution

EE Dept., Technion - Israel Inst. of Technol., Haifa, Israel

fYear

2011

fDate

15-18 May 2011

Firstpage

2593

Lastpage

2596

Abstract

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different types of synchronizers were measured and compared. The standard library FF is demonstrated to have lower tau value than various feedback flip-flops.

Keywords

CMOS integrated circuits; calibration; MTBF degradation; bulk CMOS process; calibration circuit; digital on-chip measurement system; feedback flip-flop; mean between time failure degradation; on-chip metastability measurement circuit; size 65 nm; standard library FF demonstration; synchronizer metastability measurement; technology scaling; voltage 1.1 V; Clocks; Frequency measurement; Latches; Libraries; Logic gates; Semiconductor device measurement; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5938135

Filename

5938135