Architectural and multiprocessor design verification of the PowerPC 604 data cache

The PowerPC 604 microprocessor has high performance 32-bit implementation, which is optimized to produce compact code while adhering to RISC philosophy. The PowerPC 604 microprocessor can sustain a maximum issue rate of 4 instructions per cycle. The data cache of the 604 is a 16 KB four-way set-associative non-blocking cache which contains MESI states (M: Modified, E: Exclusive-unmodified, S: Shared, I: Invalid), a reservation bit with its reservation address register, an independent snoop port, WIMG (W: cache write policy, I: cacheability, M: coherency mode, G: protection against speculative access) support logic, and parity bits. The 604 has an on-chip phase-locked loop to provide different Processor/Bus clock ratios to simplify the system design while using a 100 MHz processor clock. The data cache to BIU (Bus Interface Unit) interface can handle different Processor/Bus clock ratios. The architecture and multiprocessor verification for the PowerPC 604 data cache systematically checks the data cache architecture, logic, and implementation correctness and provides the assurance that the PowerPC 604 microprocessor´s aggressive hardware and software implementation is carried out correctly in the uniprocessor and multiprocessor environment