• DocumentCode
    1998747
  • Title

    Macrocell-level compaction with automatic jog introduction

  • Author

    Herrigel, A. ; Kamm, J. ; Fichtner, W.

  • Author_Institution
    Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
  • fYear
    1989
  • fDate
    2-4 Oct 1989
  • Firstpage
    536
  • Lastpage
    539
  • Abstract
    A novel algorithm for compacting a VLSI chip on the macrocell level is presented. Compared to previous algorithms, the technique can handle larger designs, produces higher-quality output, and reduces designer intervention as much as possible. Jogs are automatically introduced in the connecting wires to achieve the needed flexibility for placing cells into optimal positions
  • Keywords
    VLSI; circuit layout CAD; VLSI chip; automatic jog introduction; cell placement; connecting wires; macrocell level compaction; optimal positions; Algorithm design and analysis; Circuits; Compaction; Data structures; Joining processes; Laboratories; Production; Routing; Very large scale integration; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-1971-6
  • Type

    conf

  • DOI
    10.1109/ICCD.1989.63424
  • Filename
    63424
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1998747