Highly reliable double well in thin p/sup -/ on p/sup +/ epitaxial wafer for logic-embedded DRAM

Author

Yamashita, T. ; Komori, S. ; Horita, K. ; Kawasaki, Y. ; Inoue, Y. ; Nishimura, T.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

673

Lastpage

676

Abstract

A highly reliable double well using an epitaxial wafer with a thin p/sup -/-epilayer on a p/sup +/-substrate was developed. The thickness of an epilayer was optimized to ensure sufficiently high soft-error and latchup immunity. Furnace annealing after high-energy ion implantation was performed to enhance the gate-oxide reliability, and low junction leakage was also provided. This process is suitable especially for logic-DRAM merged devices which require all of these characteristics.

Keywords

CMOS logic circuits; DRAM chips; annealing; integrated circuit reliability; ion implantation; semiconductor epitaxial layers; double well; furnace annealing; gate-oxide reliability; high-energy ion implantation; junction leakage; latchup immunity; logic-embedded DRAM; p/sup +/-substrate; p/sup -/-epitaxial wafer; soft-error immunity; Annealing; CMOS logic circuits; Capacitors; Furnaces; Ion implantation; Logic circuits; Logic devices; Oxidation; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650473

Filename

650473