Design Methodology For Optimizing Gate Driven ESD Protection Circuits In Submicron Cmos Processes

This report describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS) protection scheme has been presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDNMOS is effective even for small analog/mixed-signal designs. SPICE simulation is used to optimize the design. High ESD performance of PDNMOS protection in both non-silicided and silicided submicron processes has been demonstrated.