Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor

Modern verification methodologies encourage designing testbench components for vertical re-use. In advanced microprocessor designs, multiple testbenches may be used to exercise the processorpsilas memory system. For microprocessors that support shared memory multiprocessing, the range of testbenches to be considered for implementation can be delineated along two axes: one representing the degree of vertical integration, running from an individual unit to the full core, and the other representing the number of cores present in the MP system. Candidate testbenches are selected from this space and used to test memory system functions including cache coherence, correct execution of self-modifying code, and memory consistency. Creating a successful testbench architecture that supports checking the conformance of the processor to the underlying memory consistency model requires a significant delta above the requirements for checking other functionality. However, this is especially critical for architectures such as AMD64, in which a more intuitive memory consistency model (compared to relaxed schemes) is provided to the programmer at the cost of additional hardware. A case study is presented in which components of a load/store unit testbench lacking support for memory consistency checking are modified to support memory consistency checking for testbenches representing higher levels of vertical integration and multiprocessing. Issues related to both stimulus and the results checking interface are discussed.