SEU error rates in advanced digital CMOS

Author

Massengill, L.W. ; Alles, M.L. ; Kerns, S.E.

Author_Institution

Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA

fYear

1993

fDate

13-16 Sep 1993

Firstpage

546

Lastpage

553

Abstract

Single-event error rate analysis of radiation-hardened CMOS memory parts is presented. The statistical distribution on device processing parameters is shown to explain the non-ideal error cross-section data observed in contemporary six-transistor SRAMs designed for space-based operation. A procedure for evaluating the expected error rate for these parts is presented and applied to a typical data set. The method, which arises from a development of the upset rate convolution integral, can be applied in a generic fashion using conventional ground-based test data to provide a realistic upset-rate estimate for space flight conditions

Keywords

CMOS integrated circuits; SRAM chips; aerospace instrumentation; integrated circuit testing; radiation hardening (electronics); statistical analysis; CMOS memory parts; SEU error rates; advanced digital CMOS; device processing parameters; expected error rate; generic fashion; ground-based test data; nonideal error cross-section data; radiation-hardened; single-event error rate analysis; six-transistor SRAMs; space flight conditions; space-based operation; statistical distribution; typical data set; upset rate convolution integral; upset-rate estimate; Computer errors; Cyclotrons; Error analysis; Integrated circuit modeling; Particle measurements; Read-write memory; Silicon; Single event upset; Statistical distributions; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on

Conference_Location

St. Malo

Print_ISBN

0-7803-1793-9

Type

conf

DOI

10.1109/RADECS.1993.316521

Filename

316521