DocumentCode
2004111
Title
SRAM test using on-chip dynamic power supply current sensor
Author
Liu, Jian ; Makki, Rafic Z.
Author_Institution
Fujitsu Labs. Ltd., San Jose, CA, USA
fYear
1998
fDate
24-25 Aug 1998
Firstpage
57
Lastpage
63
Abstract
We present an overview of power supply current testing of SRAMs and propose a test method to improve the CMOS SRAM test efficiency by using on-chip dynamic power supply current sensors. It is shown that the test method provides full observability of cell switching and allows for a significant reduction in test time. The test length is O(n) including coupling faults
Keywords
CMOS memory circuits; SRAM chips; design for testability; electric current measurement; electric sensing devices; integrated circuit testing; logic testing; CMOS SRAM; IDDQ testability; IDDT testability; SRAM testing; cell switching observability; onchip dynamic current sensor; power supply current sensor; static RAM; test time reduction; CMOS logic circuits; Circuit faults; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Integrated circuit testing; Logic testing; Power supplies; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-8494-1
Type
conf
DOI
10.1109/MTDT.1998.705947
Filename
705947
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