Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer

Author

DuBois, David ; DuBois, Andrew ; Connor, Carolyn ; Poole, Steve

fYear

2008

fDate

14-15 April 2008

Firstpage

239

Lastpage

247

Abstract

Double precision floating point Sparse Matrix-Vector Multiplication (SMVM) is a critical computational kernel used in iterative solvers for systems of sparse linear equations. The poor data locality exhibited by sparse matrices along with the high memory bandwidth requirements of SMVM result in poor performance on general purpose processors. Field Programmable Gate Arrays (FPGAs) offer a possible alternative with their customizable and application-targeted memory sub-system and processing elements.

Keywords

field programmable gate arrays; iterative methods; parallel machines; reconfigurable architectures; sparse matrices; vectors; FPGA; application-targeted memory sub-system; double precision floating point SMVM; field programmable gate arrays; iterative solver; reconfigurable supercomputer; sparse linear equations; sparse matrix-vector multiplication; Bandwidth; Character generation; Field programmable gate arrays; Frequency; Iterative methods; Kernel; Laboratories; Linear systems; Sparse matrices; Supercomputers; FPGA; Iterative methods; Reconfigurable hardware; Sparse Matrix-Vector Multiplication;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on

Conference_Location

Palo Alto, CA

Print_ISBN

978-0-7695-3307-0

Type

conf

DOI

10.1109/FCCM.2008.53

Filename

4724906