Reconfigurable Computing Cluster Project: Phase I Brief

Author

Schmidt, Andrew G. ; Kritikos, William V. ; Datta, Siddhartha ; Sass, Ron

Author_Institution

Univ. of North Carolina at Charlotte, Charlotte, NC, USA

fYear

2008

fDate

14-15 April 2008

Firstpage

300

Lastpage

301

Abstract

This short paper aims to describe a number of recent developments and report some key performance results. One development is additional functionality added to the custom networking board that was not originally anticipated or reported. The two other developments include Spirit´s programming model for computational scientists, and the performance of two compute accelerators (an FPU and e^-x) that have been implemented.

Keywords

data communication; field programmable gate arrays; floating point arithmetic; local area networks; reconfigurable architectures; FPU; Spirit programming model; compute accelerators; custom networking board; functionality; reconfigurable computing cluster; Bit error rate; Bit rate; Cables; Cities and towns; Computational modeling; Computer networks; Field programmable gate arrays; Programming profession; Testing; Universal Serial Bus; RCC Project; Reconfigurable Computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on

Conference_Location

Palo Alto, CA

Print_ISBN

978-0-7695-3307-0

Type

conf

DOI

10.1109/FCCM.2008.12

Filename

4724925

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2005158