A practical method of clock synchronization in 2-out-of-3 system

We expound an operable method derived from convergence-nonaveraging algorithm to solve the problem of clock synchronization in 2-out-of-3 system in engineering application. Because of the high reliable and safe requirements, the drift rate of synchronized logic clock must be as small as possible. We use the minimum offset to compute the adjusted value. Through the simulation both in software and hardware, the maximum drift rate is less than 0.1% and the maximum synchronous cycle is less than 6 cycles.