Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures

This paper presents a simulator and an architecture generator to exploit coarse-grained reconfigurable arrays (CGRAs). The simulator is able to execute and dynamically schedule to the 1-D array the instructions in the static single assignment (SSA) intermediate representation output by the compiler or after the TRS step. This tool accepts a textual description of a CGRA and generates the VHDL code ready for logic synthesis.