DocumentCode
2006002
Title
Two step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact-Penetrating Cellplate (SABPEC) for 64MbDRAM STC Cell
Author
Itob, H. ; Miyagawa, Y. ; Takahashi, M. ; Mitsuhashi, T. ; Kimura, Y. ; Endoh, A. ; Nagatomo, Y. ; Yoshimaru, M. ; Ichikawa, F. ; Ino, M.
Author_Institution
Oki Electric Industry Co., Japan
fYear
1991
fDate
28-30 May 1991
Firstpage
9
Lastpage
10
Keywords
Capacitance; Capacitors; Conductivity; Etching; Isolation technology; Rough surfaces; Shape; Surface morphology; Surface resistance; Surface roughness;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on
Conference_Location
Oiso, Japan
Type
conf
DOI
10.1109/VLSIT.1991.705964
Filename
705964
Link To Document