DocumentCode
2008570
Title
A fast and low power multiplier architecture
Author
Abu-Shama, E. ; Maaz, M.B. ; Bayonmi, M.A.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Volume
1
fYear
1996
fDate
18-21 Aug 1996
Firstpage
53
Abstract
In this paper a new multiplier architecture is proposed for low power and high speed applications. It is based on generating all partial products in one step, then summing these partial products using binary tree network. This reveals a speedup of more than 50% than the array multiplier for (32×32) bit multiplication. Computer simulation with HSPICE shows that the new proposed architecture has better speed and power performance
Keywords
SPICE; circuit analysis computing; delays; multiplying circuits; trees (mathematics); 32 bit; HSPICE; binary tree network; high speed applications; multiplier architecture; partial products; power performance; time delay; Application software; Arithmetic; Array signal processing; Binary trees; Computer architecture; Computer simulation; Delay effects; Propagation delay; Signal processing algorithms; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location
Ames, IA
Print_ISBN
0-7803-3636-4
Type
conf
DOI
10.1109/MWSCAS.1996.594026
Filename
594026
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