Accuracy of filtered traces

Author

Das, Sajal K. ; Johnson, Eric E.

Author_Institution

Klipsch Dept. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA

fYear

1995

fDate

28-31 Mar 1995

Firstpage

82

Lastpage

86

Abstract

Reducing the size of large address traces by “filtering” them through a small direct-mapped cache is a useful technique for making more efficient use of both secondary storage and processors used for trace-driven simulation. However, when filtered traces are used to drive cache simulators, the distortion introduced by such filtering can produce substantial errors in the miss ratios obtained, despite earlier reports to the contrary. We present the results of a systematic study of such errors, including a model for compensating for some errors

Keywords

cache storage; computer architecture; discrete event simulation; address traces; cache simulators; direct-mapped cache; filtered traces; miss ratios; secondary storage; trace-driven simulation; Cache memory; Cache storage; Computational modeling; Computer errors; Computer simulation; Drives; Information filtering; Information filters; Laboratories; Parallel architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-2492-7

Type

conf

DOI

10.1109/PCCC.1995.472507

Filename

472507