Title :
Scheduling unequal length tests in high performance VLSI system implementations
Author :
Sayah, John ; Kime, Charles R.
Author_Institution :
IBM, Hopewell Junction, NY, USA
Abstract :
Testing high-performance VLSI systems containing pipelines and multifunctional units is considered. An efficient heuristic-based algorithm is presented for scheduling tests in systems requiring unequal number of tests (UNT) for the test function. Performance results for an experimental implementation of the algorithm are presented
Keywords :
VLSI; automatic testing; integrated circuit testing; parallel algorithms; scheduling; heuristic-based algorithm; high performance VLSI; multifunctional units; performance results; pipelines; scheduling; test function; unequal length tests; unequal number of tests; Clocks; Design for testability; Heuristic algorithms; Modems; Parallel processing; Pipeline processing; Processor scheduling; Scheduling algorithm; System testing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63429
