An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications

The authors present a reformulation based architecture for threshold selection in adaptive foward error correction (FEC) decoding in wireless applications. The reformulation technique results in an efficient VLSI architecture with a significant reduction in hardware complexity. The paper describes the reformulation technique, its applications on the architecture for adaptive forward error correction (FEC) decoding algorithm and its implementations. We demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric unit (PMU).