Line Edge Roughness (LER) correlation and dielectric reliability with Spacer-Defined Double Patterning (SDDP) at 20nm half pitch

Author

Siew, Yong Kong ; Stucchi, Michele ; Versluijs, Janko ; Roussel, Philippe ; Kunnen, Eddy ; Pantouvaki, Marianna ; Beyer, Gerald P. ; Tokei, Zsolt

Author_Institution

IMEC vzw, Leuven, Belgium

fYear

2011

fDate

8-12 May 2011

Firstpage

1

Lastpage

3

Abstract

50% Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent Dielectric Breakdown (TDDB) lifetime, which was also predicted by simulations. Comparison of TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35nm HP Cu interconnects confirms that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.

Keywords

electric breakdown; etching; lithography; reliability; Cu interconnects; dielectric reliability; half pitch interconnects; line edge roughness correlation; litho-etch-litho-etch pattern; size 20 nm; size 35 nm; spacer-defined double patterning; time-dependent dielectric breakdown lifetime; Acceleration; Copper; Correlation; Predictive models; Reliability; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International

Conference_Location

Dresden

ISSN

pending

Print_ISBN

978-1-4577-0503-8

Type

conf

DOI

10.1109/IITC.2011.5940296

Filename

5940296