MOS current mode logic: design, optimization, and variability

Author

Hassan, Hassan ; Anis, Mohab ; Elmasry, Mohamed

Author_Institution

Waterloo Univ., Ont., Canada

fYear

2004

fDate

12-15 Sept. 2004

Firstpage

247

Lastpage

250

Abstract

An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18μm process, at which the average error is within 7% between our formulation and HSPICE.

Keywords

CMOS logic circuits; circuit optimisation; current-mode circuits; integrated circuit design; logic design; 0.18 micron; 2-level MCML circuits; CMOS process; HSPICE; MOS current mode logic; benchmark testing; high-speed microprocessor application; optical communication application; power dissipation; Benchmark testing; CMOS process; CMOS technology; Design optimization; Logic circuits; Logic design; Microprocessors; Optical fiber communication; Power dissipation; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2004. Proceedings. IEEE International

Print_ISBN

0-7803-8445-8

Type

conf

DOI

10.1109/SOCC.2004.1362424

Filename

1362424