Impact of TSV proximity on 45nm CMOS devices in wafer level

Author

Cho, Sungdong ; Kang, Sinwoo ; Park, Kangwook ; Kim, Jaechul ; Yun, Kiyoung ; Bae, Kisoon ; Lee, Woon Seob ; Ji, Sangwook ; Kim, Eunji ; Kim, Jangho ; Park, Yeong L. ; Jung, ES

Author_Institution

Syst. LSI, Samsung Electron. Co., Ltd., Yongin, South Korea

fYear

2011

fDate

8-12 May 2011

Firstpage

1

Lastpage

3

Abstract

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using `via middle´ process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.

Keywords

CMOS integrated circuits; copper; modules; silicon; three-dimensional integrated circuits; wafer level packaging; BEOL module process; CMOS device; Cu-Si; TSV proximity; backend of line module process; electrical measurement; size 45 nm; through-silicon via proximity; via middle process; wafer level; CMOS integrated circuits; Electric variables measurement; Logic gates; Performance evaluation; Stress; Threshold voltage; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International

Conference_Location

Dresden

ISSN

pending

Print_ISBN

978-1-4577-0503-8

Type

conf

DOI

10.1109/IITC.2011.5940326

Filename

5940326