Rapid energy estimation of computations on FPGA based soft processors

FPGA based soft processors are an attractive option for implementing embedded applications. As energy efficiency has become a key performance metric, techniques that can quickly and accurately obtain the energy performance of these soft processors are needed. While low-level simulation based on traditional FPGA design flow is too time consuming for obtaining such energy performance, we propose a methodology based on instruction level energy profiling. We first analyze the energy dissipation of various instructions. An energy estimator is built using this information. To illustrate the effectiveness of our approach, the energy performance of several FFT and matrix multiplication software programs running on a state-of-the-art soft processor is evaluated using the estimator. Compared with the results obtained through low-level simulation, an average estimation error of 5.9% is observed in our experiments.