FPGA-efficient phase-to-I/Q architecture

Author

Janiszewski, Ireneusz ; Meuth, Hermann ; Hoppe, Bernhard

Author_Institution

Univ. of Appl. Sci., Darmstadt, Germany

fYear

2004

fDate

12-15 Sept. 2004

Firstpage

373

Lastpage

376

Abstract

A hybrid architecture for digital phase-to-inphase/quadrature (I/Q) at constant-magnitude transformers is presented. The design may be efficiently implemented in FPGA. Starting from the well established co-ordinate rotation digital computer (CORDIC) algorithm, and from look-up table (LUT) schemes, optimum hybrid configurations are derived. Via fully synthesizable HDL models, portability and reusability are ensured. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources and is suitable also for multi-phase implementations.

Keywords

digital arithmetic; field programmable gate arrays; hardware description languages; logic design; table lookup; CORDIC algorithm; FPGA; HDL models; LUT-CORDIC architecture; constant-magnitude transformers; coordinate rotation digital computer; design partitioning; digital Quadrature; digital phase-to-Inphase; look-up table; phase-to-I/Q architecture; Algorithm design and analysis; Computer architecture; Equations; Hardware; Partitioning algorithms; Signal generators; Signal processing; Signal processing algorithms; Table lookup; Transformers;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2004. Proceedings. IEEE International

Print_ISBN

0-7803-8445-8

Type

conf

DOI

10.1109/SOCC.2004.1362468

Filename

1362468