Title :
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture
Author :
Zorian, Yervant ; Jarwala, Najmi
Author_Institution :
AT&T Bell Lab., Princeton, NJ, USA
Abstract :
A unified solution to the problems that arise in the design, development, and test of VLSI processors is offered. The JTAG/IEEE P1149.1 standard boundary-scan architecture is proposed as the basis for designing testable, defect-tolerant, VLSI processors. The test access port (TAP) provided by the boundary-scan architecture is used to control and repair the microprogram control unit, as well as to control and observe key control and data values. Built-in self-test and boundary-scan are used to solve other test problems. The TAP is also used to provide a measure of defect tolerance
Keywords :
VLSI; circuit layout CAD; fault tolerant computing; integrated circuit testing; standards; JTAG/IEEE P1149.1 standard; boundary-scan architecture; built-in self-test; control values; data values; defect tolerance; defect-tolerant VLSI processors; fault tolerant VLSI processors; microprogram control unit; test access port; testable VLSI processors; Automatic testing; Built-in self-test; Debugging; Design for testability; Fault tolerance; Manufacturing; Monitoring; Registers; System testing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63432
