• DocumentCode
    2012020
  • Title

    Requirements for practical IDDQ testing of deep submicron circuits

  • Author

    Walker, D.M.H.

  • Author_Institution
    Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    15
  • Lastpage
    20
  • Abstract
    This paper describes the requirements that quiescent current (I DDQ) testing must meet in order to continue being useful in the face of rising background currents. Using projections from the 1999 International Technology Roadmap for Semiconductors, several different techniques are evaluated to determine their usefulness in future technologies
  • Keywords
    CMOS integrated circuits; VLSI; integrated circuit testing; leakage currents; CMOS; IDDQ testing; International Technology Roadmap for Semiconductors; background currents; deep submicron circuits; quiescent current testing; Circuit faults; Circuit optimization; Circuit testing; Current measurement; Delay; Feedback; Heat sinks; High performance computing; Power supplies; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on
  • Conference_Location
    Montreal, Que.
  • Print_ISBN
    0-7695-0637-2
  • Type

    conf

  • DOI
    10.1109/DBT.2000.843685
  • Filename
    843685
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2012020