Synthesis and high level optimisation of multidimensional dataflow actor networks on FPGA

This paper presents a new dataflow graph based approach for modelling, rapidly implementing, and performing high level optimization of embedded systems including dedicated pipelined hardware components. This overcomes problems with current approaches which cannot achieve both pipelined circuit implementation and flexibility for high level optimization. A new dataflow modeling technique is presented, in conjunction with an enhanced component network synthesis approach. This technique is applied to a normalized lattice filter example, demonstrating the capability for significant circuit performance improvements, a more intelligent directed synthesis flow and increased implementation flexibility.