FPGA implementation of an IF transceiver for OFDM-based WLAN

The paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for the HIPERLAN/2 standard, but most of the work can be generalized to IEEE 802.11a/g standards. The system is composed of three main blocks (autocorrelator, CORDIC, and FFT processor) that are used in different time intervals to perform all the required operations. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is reused to estimate frequency offset, to compensate that frequency and to calculate the division in the channel estimation stage. Finally, the FFT/IFFT processor also uses its complex-number multiplier to perform the channel compensation of the received OFDM symbols. The whole IF transceiver fits in a low cost FPGA, an XC3S400-4 Spartan III device.