An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip

Author

Zhang, Xun ; Rabah, Hassan ; Weber, Serge

Author_Institution

Lab. d´´Instrum. Electron. de Nancy, Nancy Univ., Vandoeuvre-les-Nancy

fYear

2008

fDate

7-9 April 2008

Firstpage

499

Lastpage

502

Abstract

in this paper, we introduce an auto-adaptation method for reconfigurable system-on-chip (SoCs) architectures. The approach is based on joint dynamic frequency scaling and the partial and dynamic reconfiguration technique. The method aims the enhancement of the global auto-adaptability of SoCs in terms of energy, efficiency and scalability. The auto-adaptation method is described and tested with the decompression algorithm (IDWT) of JPEG2000 application targeting virtex-4 FPGAs of Xilinx.

Keywords

data compression; field programmable gate arrays; image coding; logic design; reconfigurable architectures; system-on-chip; FPGA; JPEG2000 application; auto-adaptation method; decompression algorithm; dynamic frequency scaling; dynamic reconfiguration; partial reconfiguration; reconfigurable architecture; system-on-chip; Bandwidth; Clocks; Computer architecture; Equations; Field programmable gate arrays; Frequency; Hardware; Power system management; System-on-a-chip; Vehicle dynamics; Partial reconfiguration; auto-adaptation; dynamic frequency scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual

Conference_Location

Montpellier

Print_ISBN

978-0-7695-3291-2

Electronic_ISBN

978-0-7695-3170-0

Type

conf

DOI

10.1109/ISVLSI.2008.79

Filename

4556850