An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES

Author

Li, Chung-Yi ; Chien, Chih-Feng ; Hong, Jin-Hua ; Chang, Tsin-Yuan

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu

fYear

2008

fDate

7-9 April 2008

Firstpage

503

Lastpage

506

Abstract

MixColumns/InvMixColumns dominates both the logic resource and the critical delay in advanced encryption standard (AES) hardware implementation with direct mapping S-boxes. The proposed decomposition method optimizes the area and the delay of integrated MixColumns/InvMixColumns circuit. Theoretically, the proposed short-path circuit reduces the area up to 42% with the same 5 XOR gates delay (Y.-K. Lai et al, 2004) in critical path. When synthesized in a TSMC 0.18 mum CMOS technology, the proposed short-path circuit has the top performance measured in AT and AT².

Keywords

CMOS integrated circuits; cryptography; AT2; TSMC CMOS technology; XOR gates delay; advanced encryption standard hardware; area-delay product design; critical delay; decomposition method; direct mapping S-boxes; integrated InvMixColumns circuit; integrated MixColumns circuit; logic resource; short-path circuit; CMOS technology; Cryptography; Delay; Hardware; Integrated circuit measurements; Integrated circuit synthesis; Integrated circuit technology; Logic; Optimization methods; Product design; Area-Delay Product; circuit optimization; cryptography; decomposition in InvMixColumn;

fLanguage

English

Publisher

ieee

Conference_Titel

Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual

Conference_Location

Montpellier

Print_ISBN

978-0-7695-3291-2

Electronic_ISBN

978-0-7695-3170-0

Type

conf

DOI

10.1109/ISVLSI.2008.81

Filename

4556851