Measurement of wall voltage in reset discharge of plasma display panel

Summary form only given, as follows. In AC plasma display, it is very important to quantify the wall voltage induced by the wall charge accumulated on the dielectric surface. If we know the quantities of the wall voltage in each period of every sequence, reset period, address period and sustain period, then it helps to design the optimal driving waveform for a high efficiency plasma display. The purpose of this study is to experimentally investigate the exact wall voltage profiles at each period of every sequence and then provide the basic data to a driving sequence designer. We develop a new method to measure the wall voltage with a versatile driving simulator system.