Title :
Synthesis for arithmetic built-in self-test
Author :
Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
Arithmetic built-in self-test (BIST) is a favorable test method for data paths that include adders, subtracters, and other arithmetic units. With these functional units, accumulator structures are configured to generate test patterns and compact test responses. This paper presents a method to synthesize data paths that are well-suited for arithmetic BIST. The key part of this approach is an assignment procedure that takes into account structural properties which are advantageous for arithmetic BIST. The resulting circuits have the same speed and require about the same area as circuits that have been synthesized without testability considerations
Keywords :
adders; application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; digital arithmetic; integrated circuit testing; logic testing; accumulator structures; adders; arithmetic built-in self-test; arithmetic units; assignment procedure; compact test responses; data paths; structural properties; subtracters; test patterns; testability considerations; Adders; Arithmetic; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Registers; System testing; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843841
