• DocumentCode
    2014972
  • Title

    Fault escapes in duplex systems

  • Author

    Mitra, Subhasish ; Saxena, Nirmal R. ; McCluskey, Edward J.

  • Author_Institution
    Dept. of Electr. Eng., Stanford Univ., CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    453
  • Lastpage
    458
  • Abstract
    Hardware duplication techniques are widely used for concurrent error detection in dependable systems to ensure high availability and data integrity. These techniques are vulnerable to common-mode failures (CMFs). Use of duplex systems with diverse implementations of the two modules has been proposed in the past for protection against CMFs. In this paper, we define a category of faults, called non-self-testable faults that undermine the data integrity of dependable systems. These faults produce identical errors at the outputs of the two modules of a duplex system and can potentially be caused by CMFs. The main contributions of this paper are: (1) techniques that identify non-self-testable faults in duplex systems, and (2) design methods that reduce the number of non-self-testable faults by test point insertion. We show that our algorithm for identifying non-self-testable faults runs orders of magnitude faster than exact techniques with minimal loss of accuracy. Also, there is a significant reduction in the number of test points required for duplex systems with diverse implementations compared to duplex systems with identical implementations. Thus, we can detect common-mode failures in diverse duplex systems using very few test points. These results are especially useful for systems with user-programmable logic elements that enhance the practicality of using diverse designs in duplex systems
  • Keywords
    built-in self test; comparators (circuits); error detection; failure analysis; fault diagnosis; logic testing; modules; redundancy; common-mode failures; concurrent error detection; data integrity; duplex systems; hardware duplication techniques; non-self-testable faults; test point insertion; test points; user-programmable logic elements; Availability; Computer errors; Concurrent computing; Design methodology; Fault detection; Fault diagnosis; Hardware; Logic design; Protection; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2000. Proceedings. 18th IEEE
  • Conference_Location
    Montreal, Que.
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0613-5
  • Type

    conf

  • DOI
    10.1109/VTEST.2000.843878
  • Filename
    843878