• DocumentCode
    2017544
  • Title

    High speed merged multiplication

  • Author

    Islam, Farhad F. ; Tamaru, Keikichi

  • Author_Institution
    Dept. of Electron., Kyoto Univ., Japan
  • Volume
    1
  • fYear
    1993
  • fDate
    27-30 April 1993
  • Firstpage
    377
  • Abstract
    The authors propose a hardware algorithm for merged array multiplication. It offers an impressive improvement in latency when compared with a conventional scheme for merged array multiplication. The cost in the form of additional VLSI area is rather small and decreases with increasing bit-size of operands.<>
  • Keywords
    VLSI; array signal processing; digital arithmetic; digital signal processing chips; merging; VLSI area; hardware algorithm; latency; merged array multiplication;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on
  • Conference_Location
    Minneapolis, MN, USA
  • ISSN
    1520-6149
  • Print_ISBN
    0-7803-7402-9
  • Type

    conf

  • DOI
    10.1109/ICASSP.1993.319134
  • Filename
    319134
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2017544