• DocumentCode
    2017555
  • Title

    WCET analysis considering contention on memory bus in COTS-based multicores

  • Author

    Dasari, Dakshina ; Nelis, Vincent ; Andersson, Björn

  • Author_Institution
    CISTER-ISEP Res. Centre, Polytech. Inst. of Porto, Porto, Portugal
  • fYear
    2011
  • fDate
    5-9 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.
  • Keywords
    embedded systems; multiprocessing systems; processor scheduling; resource allocation; storage management; COTS-based multicore system; WCET analysis; embedded system; low-level hardware resource sharing; memory bus; real-time system; task scheduling; worst-case execution time; Hardware; Multicore processing; Niobium; Random access memory; Real time systems; Schedules; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Emerging Technologies & Factory Automation (ETFA), 2011 IEEE 16th Conference on
  • Conference_Location
    Toulouse
  • ISSN
    1946-0740
  • Print_ISBN
    978-1-4577-0017-0
  • Electronic_ISBN
    1946-0740
  • Type

    conf

  • DOI
    10.1109/ETFA.2011.6059176
  • Filename
    6059176