Reconfigurable architecture of adaptive median filter — An FPGA based approach for impulse noise suppression

In this paper, low complexity reconfigurable hardware architecture for adaptive median filter is proposed and a comparative study of hardware based median and adaptive median filter is presented. An efficient development of median & adaptive median filter is presented for removal of impulse noise mainly salt & pepper noise from digital Images. Performance measurement of mean square error (MSE) and peak signal-to-noise ratio (PSNR) is done to compare these two filters. This paper proposes hardware implementation which is highly required for real time execution. Field Programmable Gate Arrays (FPGAs) are widely used for real time processing where the requirements of time, speed, area, power become strict. The algorithms of these two filters are discussed in detail which is followed by FPGA based solutions. Simulation is done using Xilinx ISE 14.5 software of XILINX platform where the implementations utilize on Genesys VERTEX V FPGA Board of XC5VLX50T device family.