A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz

A synchronous 50% duty cycle divide-by-3 divider up to 6 GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the input clock signal. These cells are not stand alone, but coupled with each other. Thanks to the coupling and input current with 120° phase splitting, the outputs of the three cells are locked at the 1/3 input frequencies with 60°phase splitting, which means that the outputs are of an accurate 50% duty cycle. Injection behavior model is proposed for analysis, and some design guidelines are acquired here. This divider is fabricated in 0.18 μm CMOS process and works with a nominal supply voltage of 1.8 V. The measured results indicate that the locking range of this divider is 4 GHz (from 2.5 GHz to 6.5 GHz) at an input power of 0 dBm with about 4 mW power dissipation. As high as 28 dB second harmonic suppression of a single-ended output proves that this proposed divider realizes a true 50% duty cycle signal.