CMOS architecture of synchronous pulse-coupled neural network and its application to image processing

This paper presents a compact architecture for a CMOS implementation of a pulse-coupled neural net (PCNN) and its application to image processing. A computational style described in this article mimics a biological neural network using pulse-stream signaling and analog summation and multiplication. The pulse-stream encoding technique utilizes pulse streams to carry information and to control the analog circuitry, while storing further analog information on the time axis. The structural form of the pulse-coupled neuron is presented first, then its application to image processing and the synchronization effect between neighboring neurons are demonstrated