Dynamic power and signal integrity analysis for chip-package-board co-design and co-simulation

This paper presents global dynamic power and signal integrity analysis methodologies for chip-package-board co-design and co-simulation. The proposed methodologies are based on efficient combination of power switching activity macro-modeling with broadband multi-port model extractions. Dedicated real-life test carriers are employed for benchmarking purposes and correlation with on-wafer measurement. The results from EM simulations are fed into circuit simulator environment (Cadence) following divide-and-conquer segmentation approaches. Additionally, two different types of current activity models are used to model the digital die. The obtained simulation results are validated by comparison with time-domain and frequency-domain measurement.