Investigations of cooling solutions for three-dimensional (3D) chip stacks

Author

Matsumoto, Kaname ; Ibaraki, S. ; Sato, Mitsuhisa ; Sakuma, Keita ; Orii, Y. ; Yamada, Fumihiko

Author_Institution

ASET (Assoc. of Super-Adv. Electron. Technol.), Yamato, Japan

fYear

2010

fDate

21-25 Feb. 2010

Firstpage

25

Lastpage

32

Abstract

Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom of a silicon interposer and cooling from the peripheral of a silicon interposer were proposed and evaluated. Based on the experimentally obtained thermal resistance of lead-free (SnAg) interconnections, the cooling performances of the above two cooling solutions were investigated by modeling and the requirements were clarified.

Keywords

cooling; heat sinks; thermal resistance; three-dimensional integrated circuits; 3D chip stack cooling method; heat sink; high circuit density; lead-free interconnections; microchannel cooler; silicon interposer; thermal resistance; three-dimensional chip stacks; Cooling; Heat sinks; Heat transfer; Integrated circuit interconnections; Performance evaluation; Silicon; System performance; Thermal conductivity; Thermal resistance; Through-silicon vias; Cooling solution; interconnections; thermal resistance; three-dimensional (3D) chip stack;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Thermal Measurement and Management Symposium, 2010. SEMI-THERM 2010. 26th Annual IEEE

Conference_Location

Santa Clara, CA

ISSN

1065-2221

Print_ISBN

978-1-4244-9458-3

Electronic_ISBN

1065-2221

Type

conf

DOI

10.1109/STHERM.2010.5444319

Filename

5444319