Title :
A 6-mW 10-bit 300 ksamples/s pipeline A/D-converter
Author :
Mäntyniemi, Antti ; Rahkonen, Timo ; Ruha, Antti
Author_Institution :
Dept. of Electr. Eng., Oulu Univ., Finland
Abstract :
This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-μm CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from a 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +- 1.5 LSB and DNL +/- 0.5 LSB. The active chip area is 1.3 mm2, excluding pads
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit optimisation; integrated circuit layout; integrated circuit noise; pipeline processing; signal sampling; 0.8 mum; 10 bit; 2 mA; 2.7 V; 6 mW; CMOS technology; DNL; ENOB; INL; LSB; SNR; active chip area; analog-to-digital converter; comparator offset mismatch; current consumption; digital redundant signed digit principle; error correction; gain factor mismatch; interleaved pipeline structure; operational amplifier; power consumption minimisation; power saving scheme; resolution per stage; CMOS technology; Capacitors; Circuits; Clocks; Energy consumption; Operational amplifiers; Pipelines; Power engineering and energy; Sampling methods; Voltage;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594093
