Select transistor modulated cell array structure test for EEPROM reliability

Author

Pio, Federico ; Gomiero, Enrico

Author_Institution

Central R&D, STMicroelectron., Italy

fYear

2000

fDate

2000

Firstpage

217

Lastpage

222

Abstract

A test structure consisting of a not addressable EEPROM cell array is presented together with the measurement methodology. Accurate information on the threshold voltage distribution of the cells in the array is obtained from the transfer characteristic measured under select transistor clamping bias. We discuss in detail the working principle and the different levels of approximation, presenting several results for early process/design reliability evaluation (bake retention, control gate stress, programming pulse optimisation).

Keywords

EPROM; integrated circuit reliability; integrated circuit testing; integrated memory circuits; voltage distribution; EEPROM reliability; data retention; measurement methodology; nonvolatile memory; reliability evaluation; select transistor clamping bias; select transistor modulated cell array structure test; test structure; threshold voltage distribution; transfer characteristic measure; Circuit testing; Clamps; Convolution; EPROM; Large Hadron Collider; Proportional control; Shape; Stress control; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on

Print_ISBN

0-7803-6275-7

Type

conf

DOI

10.1109/ICMTS.2000.844434

Filename

844434