A practical approach for circuit routing on dynamic reconfigurable devices

Author

Ahmadinia, Ali ; Bobda, Christophe ; Ding, Ji ; Majer, Mateusz ; Teich, Jürgen ; Fekete, Sándor P. ; van Der Veen, Jan C.

Author_Institution

Dept. of Comput. Sci. 12, Erlangen-Nurnberg Univ., Erlangen, Germany

fYear

2005

fDate

8-10 June 2005

Firstpage

84

Lastpage

90

Abstract

Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial re configurability is a new challenging problem. A network-on-chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.

Keywords

field programmable gate arrays; network routing; reconfigurable architectures; system-on-chip; 1-dimensional network; FPGA online routing; circuit routing algorithm; dynamic NoC; dynamic reconfigurable devices; logic resources; network-on-chip; partial reconfigurability; Circuit topology; Field programmable gate arrays; Logic; Multiprocessor interconnection networks; Network interfaces; Network topology; Network-on-a-chip; Resource management; Routing; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 2005. (RSP 2005). The 16th IEEE International Workshop on

ISSN

1074-6005

Print_ISBN

0-7695-2361-7

Type

conf

DOI

10.1109/RSP.2005.7

Filename

1509437