Title :
Semi-unified Caches
Author :
Drach, Nathalie ; Seznec, André
Author_Institution :
IRISA/INRIA Campus de Beaulieu, Cedex, France
Abstract :
The purpose of the semi-unified on-chip cache organization, is to use the data cache (resp. ins truction cache) as an on-chip second-level cache for instructions (resp. data). Thus the associativity de gree of both on-chip caches is artificially increased, and the cache spaces respectively devoted to instruc tions and data are dynamically adjusted. The off-chip miss ratio of a semi-unified cache built with two directmapped caches of size S is equal to the miss ratio of a unified two-way set associative cache of size 2S; yet, the hit time of this semi-unified cache is equal to the hit time of a direct-mapped cache. Trace driven simu lations show that using a direct-mapped semi-unified cache organization leads to higher overall system per formance than using usual split instruction/data cache organization.
Keywords :
Clocks; Frequency; Microprocessor chips; Parallel processing; Pipelines;
Conference_Titel :
Parallel Processing, 1993. ICPP 1993. International Conference on
Conference_Location :
Syracuse, NY, USA
Print_ISBN :
0-8493-8983-6
DOI :
10.1109/ICPP.1993.162