Memory Reference Behavior of Compiler Optimized Programs on High Speed Architectures

High speed architectures usually employ some form of parallelism or concurrency. Parallel or concurrent execution of a program not only increases the rate at which references are issued to the memory system but also changes the behavior of these references, relative to its serial-scalar execution. This paper reports the variations in program memory reference behavior when automatically transformed by a compiler and executed on parallel and vector archirectures. Using traces of the PERFECT benchmark set, executed on on Aliiant FX180 in a single scalar processor, single vector processor, scalar multiprocessor and vector multiprocessor modes, measurements are reported for issue rates, reference locality and data sharing.