Optimized shift register design using reversible logic

Now a days, reversible logic is seeking lot of attraction due to its low power consumption. Though lot of research has been done in reversible combinational circuit design, the less work has been done in sequential logic, especially shift registers. In this work we proposed a new D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of gates. Using this proposed D flip-flop we also proposed efficient shift registers.