• DocumentCode
    20392
  • Title

    Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels

  • Author

    Zhuo Wang ; Kyong Ho Lee ; Verma, Naveen

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA
  • Volume
    23
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    1459
  • Lastpage
    1470
  • Abstract
    We present an approach for overcoming computational errors at run time that originate from static hardware faults in digital processors. The approach is based on embedded machine-learning stages that learn and model the statistics of the computational outputs in the presence of errors, resulting in an error-aware model for embedded analysis. We demonstrate, in hardware, two systems for analyzing sensor data: 1) an EEG-based seizure detector and 2) an ECG-based cardiac arrhythmia detector. The systems use a small kernel of fault-free hardware (constituting <;7.0% and <;31% of the total areas respectively) to construct and apply the error-aware model. The systems construct their own error-aware models with minimal overhead through the use of an embedded active-learning framework. Via an field-programmable gate array implementation for hardware experiments, stuck-at faults are injected at controllable rates within synthesized gate-level netlists to permit characterization. The seizure detector demonstrates restored performance despite faults on 0.018% of the circuit nodes [causing bit error rates (BERs) up to 45%], and the arrhythmia detector demonstrates restored performance despite faults on 2.7% of the circuit nodes (causing BERs up to 50%).
  • Keywords
    electrocardiography; electroencephalography; embedded systems; fault diagnosis; field programmable gate arrays; learning (artificial intelligence); medical signal processing; ECG-based cardiac arrhythmia detector; EEG-based seizure detector; arrhythmia detector; computational errors; computational outputs; digital processors; embedded analysis; embedded machine-learning kernels; error-aware model; fault-free hardware; field-programmable gate array implementation; hardware experiments; sensing platforms; sensor data; static hardware faults; stuck-at faults; synthesized gate-level netlists; Brain modeling; Circuit faults; Data models; Hardware; Kernel; Support vector machines; Training; Embedded sensing; fault tolerance; hardware resiliency; machine learning; run-time error correction;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2342153
  • Filename
    6874569