A Low-Power Differential Transmission Line Interconnect Using Wafer Level Package Technology

Author

Maekawa, Takuya ; Ishii, Takahiro ; Seita, Junki ; Ito, Hiroyuki ; Okada, Kenichi ; Hatakeyama, Hideki ; Uemichi, Yusuke ; Aizawa, Takuya ; Ito, Tatsuya ; Yamauchi, Ryozo ; Masu, Kazuya

Author_Institution

Integrated Res. Inst., Yokohama

fYear

2008

fDate

12-15 May 2008

Firstpage

1

Lastpage

4

Abstract

This paper proposes a low-power on-chip transmission line interconnect (TLI) using wafer level package (WLP) technology. A 0.18 mum Si CMOS process was used to fabricate a transmitter (Tx) and a receiver (Rx). The prototype TLI with a transmission line in WLP has about 40% smaller power consumption than that with a transmission line in multilevel interconnects.

Keywords

CMOS integrated circuits; integrated circuit interconnections; low-power electronics; silicon; wafer level packaging; CMOS process; Si; differential transmission line interconnect; multilevel interconnects; on-chip transmission line interconnect; size 0.18 mum; wafer level package technology; Attenuation; CMOS process; CMOS technology; Energy consumption; Packaging; Paper technology; Power transmission lines; Resins; Transmission lines; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Propagation on Interconnects, 2008. SPI 2008. 12th IEEE Workshop on

Conference_Location

Avignon

Print_ISBN

978-1-4244-2317-0

Electronic_ISBN

978-1-4244-2318-7

Type

conf

DOI

10.1109/SPI.2008.4558361

Filename

4558361