On-chip capacitor low dropout voltage regulator implemented in 90nm CMOS technology process

A low dropout voltage regulator designed and implemented in 90nm 1P9M 3.3V CMOS technology process is presented in this paper. The design consists mainly of three stages, namely, error amplifier, efficiency boosting circuit and a power stage which utilized a power PMOS. Moreover, the design employs a solution to bulky external capacitors of the present low dropout voltage regulators with an on-chip capacitor. Compensation scheme is also used to provide fast transient and stability. Capacitors used on this design doesn´t exceed 13pF, this allows the designer to easily integrate the compensation capacitors within the LDO chip. The designed LDO has an active area of 1.14μm² and a ground current of 94.2μA and a dropout voltage of 250mV. The input voltage is ranged from 2-3.6 volts for loading current of 150mA and the output of 1.75 volts.