VLSI architectural framework for area/power performance tuning

Parametric variations in scaled technologies below 90nm will pose a major challenge for design of future high performance processors. Increasing levels of process variability in sub-90nm CMOS design has become a critical concern for performance and power constraint designs In this paper, a low-cost architectural framework for power/area performance tuning is developed. It brings the area and power consumption of a die within the acceptable range. Tuning “knobs” such as tunable gates are employed to deal with delay and power variations. This tuning technique improves the delay yield considerably with reduction in area by using Top down pass transistor logic designs.